Semiconductor integrated circuits are typically fabricated by a layering process in which several layers of material are fabricated on a surface of a wafer. Contamination on the backside of the wafer (i.e., the side of the wafer opposite to the surface being layered) is a significant contributor to problems during fabrication. In particular, contamination on the backside of the wafer may cause fabrication defects at a number of different processing steps. For example, the presence of backside contamination may cause over etching or under etching during the chemical etching process or during the chemical-mechanical polishing process (CMP). Moreover, the presence of backside contamination may also cause imaging-related defects during process steps such as photolithography, wafer inspection, or during rapid thermal annealing (RTA). Backside contamination may also be the cause of poor surface contact with the backside of the wafer during processes which utilize RF or heat transfer to the backside of the wafer such as during the etching process or RTA.
Large contamination particles may even be undesirably transferred to the front side of the wafer thereby potentially causing scratching of the front side of the wafer or the “micromasking” of a portion of the front side of the wafer. In some extreme cases, the presence of backside contamination may even cause wafers to be broken due to stress or loss of vacuum pressure during wafer handling.